EMI-ISO 7637穎立科技有限公司



ES620 Compact TLP IV-Curve System



The ES620 Compact Pulsed IV-Curve Test and Analysis System is our new development for 2015.  It is an advanced and compact pulsed IV-curve characterization system designed to simulate pulsed ESD events such as TLP, vf-TLP, HMM, HBM, EFT, and LV-Surge.  It will monitor the transient voltage and current waveforms during the pulse in ps or ns segments, and test the pre- and post-pulse status (leakage current, breakdown voltage, biasing current, static IV curve, etc…) of the device under test (DUT). Common DUT’s include protection devices, semiconductors, circuit modules, touch panel sensor, etc.

The Transmission Line Pulse (TLP) test and analysis function is designed to meet ANSI/ESD STM5.5.1-2014 test standards. Our system generates high quality rectangular pulses to devices while recording both the current through and voltage across the device.  This gives a pulsed IV curve that allows users to characterize the device’s transient response in nanosecond time windows.  Advanced automatic device failure detection methods such as leakage testing, static IV curve, and fuse and spark are incorporated.

The very fast TLP (vf-TLP) test and analysis function is designed to meet ANSI/ESD SP5.5.2-2007 test standard practice.  The vf-TLP test function is designed to simulate the CDM speed ESD event and captures the current through and voltage across the device under very high speeds (approximately 100 ps rise-time).  This allows the user to study the response speed and peak voltage of a device.

The Human Metal Model (HMM) test and analysis function is designed to meet ANSI/ESD SP5. 6-2009 test standard practice alternative test method for IC to IEC61000-4-2 system level ESD.  It gives equivalent waveform to an ideal standard waveform for low Ohmic devices and eliminates many IEC gun test problems, such as repeatability, imprecise gun tip, impedance mismatch, EMI interferences from unshielded relays, and special set-up with large ground planes and coupling planes, for component or wafer level tests.

This system features complete software control and customizable rise-time and pulse width selections, great compatibility with IVI instruments, compact size, and an affordable price.

We have 2 software developments, one based on LabVIEW and another based on Python.

Parameters ES620-25 ES620-50 ES620-100     Unit Comments
Output Voltage @ open load ± 0.5 ~ 1250 ± 0.5 ~ 2500 ± 10 ~ 5000  V  
Output Voltage Step @ 50 Ω load ± 0.25 ~ 625 ± 0.25 ~ 1250 ± 0.5 ~ 2500 V  
Min voltage step @ 50 Ω load 0.1 0.1 0.1 V  
Output Voltage Precision Better than 5 % % After self-calibration
Output current @ short load ± 0.01 ~ 25 ± 0.02 ~ 50 ± 0.04 ~ 100 A  
Output current @ 50 Ω load ± 0.005 ~ 12.5 ± 0.01 ~ 25 ± 0.02 ~ 50 A  
Peak power @ 50 Ω load ≥ 7.813  ≥ 31.25 ≥ 125 kW  
Intrinsic TLP rise-time ≤ 0.1 ≤ 0.2 ≤ 1 ns 60 ps option available on ES620-25
Other rise-time options 0.1 ~ 50 0.2 ~ 50 1 ~ 50 ns Depends on model, check table 2
Intrinsic TLP pulse width 100 ± 1     ns Default
Other pulse-width options 1 ~ 3200 2.5 ~ 1600 5 ~ 500 ns Depends on model, check table 3
Test repetition time Typical 0.5 ~ 2     s OSC, SMU and state dependent
Dimensions 347 X 300 X 145     mm  
Weight 6 8 kg  


Low Parasitic HBM/HMM/MM tester with high quality pulses

Low Parasitic HBM/HMM/MM tester with high quality pulses 

Friendly for probe station

Large Touch Panel and Firmware Upgradable

Optional Software Controlled Automated Pulse and Failure Measurement

Optional Pulsed IV and DC IV Characterization



Wafer level ESD test
PCB / package level ESD test
System / circuit module ESD test
TLP / VF-TLP option meets ANSI/ESD STM 5.5.1-2016
HMM option meets ANSI/ESD SP5.6-2009
HBM option meets ANSI/ESDA/JEDEC JS-001-2017
Safe Operation Area (SOA) test
Charge recovery time test
Differential ESD pulse injection
Touchscreen ITO trace fuse test
Touchscreen ITO trace breakdown test



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